The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
P-channel metal oxide semiconductor field effect transistors (PMOSFETs) and n-channel MOSFETs (NMOSFETs) are used in many high performance integrated circuits. Reducing contact resistance is important for further improving performance. While nickel silicide (NiSi) provides good contact resistance, NiSi includes Si which is a mid-gap work function material (0.65 eV) (similar to cobalt (Co) and titanium (Ti)) and is prone to form pipes of NiSi2, which limits performance.
A metal insulator silicon (MIS) structure has also been used to reduce contact resistance. However, the insulator (typically titanium dioxide (TiO2) or silicon dioxide (SiO2)) does not remain stable during subsequent processing.
Another approach for reducing contact resistance uses Ti metal in direct contact with Si. The Ti metal is deposited using physical vapor deposition (PVD) and requires a titanium nitride (TiN) cap deposited using chemical vapor deposition (CVD). As contact dimensions scale, the TiN cap consumes much of the contact fill and has high resistance. Manufacturers have resorted to expensive integration techniques to etch back the high resistance TiN cap and fill the contact and/or metal gate with a lower resistance metal. Both the interface resistance and contact material resistance need to be reduced.
In dual silicide integration, providing low contact resistance for NMOSFETs and PMOSFETs involves the use of different materials. Dual silicide integration was actively researched to reduce resistance between the silicide and the silicon. In this integration, a work function of the silicide is tailored to reach the band edge. The candidates are: PMOSFETs>0.8 eV using iridium (Ir), platinum (Pt) or osmium (Os) and NMOSFETs<0.3 eV using erbium (Er), ytterbium (Yb), dysprosium (Dy) or gadolinium (Gd).
Other channel materials with higher carrier mobilities have been proposed to replace silicon (Si). For example, germanium (Ge) has higher electron and hole mobilities than Si. Ge is a group IV element (like Si) and is compatible with current manufacturing facilities.
Ge PMOSFETs have been demonstrated with good performance. However, Ge NMOSFETs have suffered from poor drive current due to high parasitic resistance. A metal Fermi level at metal/Ge interfaces is pinned close to a Ge valence band, which leads to a large barrier to n-type Ge and a high contact resistance (Rs). Rs needs to be reduced in order to improve Ge NMOSFET performance and realize Ge devices.